| S.No | IP | Skillset Availability |
Includes | Package | Silicon Proven | Technology |
|---|---|---|---|---|---|---|
| 1 | GPIO | yes | 64 IO cells with fillers and Cut cells |
BGA | YES | 130/90/65/40/28 |
| 2 | Stc Cell | yes | Sch/Lay/Abstract/Lib/LEF/Datasheet | NA | YES | 90/65 |
| 3 | Memory Design/Compiler | yes | Decoders/SenseAmp/IO | BGA | NO | 65 |
| 4 | LVSTL12 | yes | DRIVER/RECEIVER | BGA | YES | 90/65 |
| 5 | HSTL15 | yes | DRIVER/RECEIVER | BGA | YES | 90/65 |
| 6 | SSTL 18/25/33-CI/II | yes | DRIVER/RECEIVER | BGA | YES | 90/65 |
| 7 | LVDS 1.25GBPS | yes | DRIVER/RECEIVER | BGA | YES | 90/65 |
| 8 | LVECL | yes | DRIVER/RECEIVER | BGA | YES | 90/65 |
| 9 | RSDS | yes | DRIVER/RECEIVER | BGA | YES | 130/90 |
| 10 | USB2.0/3.0 phy | yes | PLL+TX+RX | BGA | YES | 130/90 |
| 11 | PCIe GEN III/III/IV | yes | PLL+TX+RX/QUAD | BGA/FC | YES | 90/65/40 |
| 12 | MIPI Dphy | yes | PLL+TX+RX | BGA | YES | 90 |
| 13 | Source Synchronous(DDR) | yes | PLL+TX+RX+(Re/tm)40Lane/20Lane(3inch) | PCB | YES | 65/10 Finfet |
| 14 | Displayport | yes | PLL+TX+RX+(Re/tm)4Lane QUAD) | BGA | YES | 65 |
| 15 | HDMI2.0(1080p) | yes | PLL+TX+RX(4Lane QUAD) | BGA | YES | 65/10 |
| 16 | HSSTP | yes | PLL+TX(4-Lane QUAD) | BGA/FC | YES | 65/40 |
| 17 | High Speed PLL | yes | RO/LC VCO | BGA | YES | 130/90/65/40/16/10 |
| 18 | ADC(10 Bit/6-Bit) | yes | Pipeline/To step flash High speed | BGA | YES | 130/90 |
| 19 | DAC(10 Bit/6-Bit) | yes | Current steering Segmentation | BGA | YES | 130/90 |
| 20 | SERDES(Multi- Standard/protocol) |
yes | CEI/BaseT/KR4/XFI/SFI | BGA/FC | YES | 65/12 |