Bangalore Experience: 2-4
Description
Develop and implement Automated Test Equipment (ATE) programs to validate silicon performance and functionality. Collaborate with design and product engineers to optimize test coverage and ensure high quality, manufacturable devices.
Bangalore Experience: 4
Description
Responsible for integrating RTL modules and performing static checks like CDC and Lint using tools such as Spyglass to ensure robust and error-free designs. Collaborate with cross-functional teams to drive timely tape-outs
Bangalore Experience: 4
Description
Employ formal methods to rigorously verify design correctness, ensuring functional coverage and eliminating corner-case bugs. Develop and execute formal testbenches for complex IPs and SoCs.
Bangalore Experience: 4
Description
Execute Gate Level Simulation (GLS) to validate timing, power, and logical correctness post-synthesis. Analyze and resolve issues related to gate-level netlists and real-world conditions.
Hyderabad/Bangalore Experience: 3 to 10
Description
Drive the physical implementation of RTL to GDSII including floorplanning, placement, routing, and timing closure. Optimize performance, area, and power for advanced technology nodes.
Noida/Bangalore Experience: 2.5 to 5
Description
Design and optimize memory layouts for FinFET technologies ensuring high yield, reliability, and performance. Collaborate closely with process and circuit teams to develop advanced memory products.
Hyderabad/Bangalore Experience: 4
Description
Develop and implement DFT architectures including scan insertion, ATPG, and BIST to enhance testability and quality. Work with verification and test teams to ensure high coverage and manufacturabilit
Hyderabad/Bangalore Experience: 4+
Description
Create and execute comprehensive verification plans using UVM or similar methodologies, ensuring robust and bug-free designs. Analyze functional coverage and debug issues alongside design and architecture teams