Based on customer requirements KriSemi can provide below mixed signal IPs

Sl # IP Skillset Availability Includes Package Silicon Proven Technology
1 GPIO yes 64 IO cells with fillers and Cut cells BGA YES 130/90/65/40/28
2 Stc Cell Yes Sch/Lay/Abstract/Lib/LEF/Datasheet NA YES 90/65
3 Memory Design/Compiler Yes Decoders/SenseAmp/IO BGA NO 65
4 LVSTL12 Yes DRIVER/RECEIVER BGA YES 90/65
5 HSTL15 Yes DRIVER/RECEIVER BGA YES 90/65
6 SSTL 18/25/33-CI/CII Yes DRIVER/RECEIVER BGA YES 90/65
7 LVDS 1.25GBPS Yes DRIVER/RECEIVER BGA YES 90/65
8 LVPECL Yes DRIVER/RECEIVER BGA YES 90/65
9 RSDS Yes DRIVER/RECEIVER BGA YES 130/90
10 USB2.0/3.0 phy Yes PLL+TX+RX BGA YES 130/90
11 PCIe-GEN I/II/III/IV Yes PLL+TX+RX/QUAD BGA/FC YES 90/65/40
12 MIPI Dphy Yes PLL+TX+RX BGA YES 90
13 Source Synchronous(DDR) Yes PLL+TX+RX+Vcm+Rterm(40Lane/20Lane) 3inch PCB YES 65/10 Finfet
14 Displayport Yes PLL+TX+RX+Rterm(4-Lane QUAD) BGA YES 65
15 HDMI2.0(1080p) Yes PLL+TX+RX(4-Lane QUAD) BGA YES 65/10
16 HSSTP Yes PLL+TX(4-Lane QUAD) BGA/FC YES 65/40
17 High Speed PLL Yes RO/LC VCO BGA YES 130/90/65/40/16/10
18 ADC(10 Bit/6-Bit) Yes Pipeline/ To step flash High speed BGA YES 130/90
19 DAC(10 Bit/6-Bit) Yes Current steering Segmentation BGA YES 130/90
20 SERDES(Multi-Stadard/protocol) Yes CEI/BaseT/KR4/XFI/SFI BGA/FC YES 65/12