Physical design

  • Floor planning, power planning and IO planning

  • DRC/ LVS testing and verification

  • Performance analysis such as power, signal integrity, and IR

  • Die area estimation of macros/IOs and estimation based on pads and logic block area

  • Full chip design with packaging-part and closure
  • Design partition and hardening

  • Signoff Timing Closure

  • Low power design implementation

  • Physical Verification

  • Static Timing Analysis (STA)

  • Deep node FinFET technologies